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  1. List of HTTP status codes - Wikipedia › wiki › List_of_HTTP_status_codes

    This is a list of Hypertext Transfer Protocol (HTTP) response status codes. Status codes are issued by a server in response to a client's request made to the server. It includes codes from IETF Request for Comments (RFCs), other ...

  2. Harmonic damper - Wikipedia › wiki › Harmonic_damper
    • Need
    • Torsional Crankshaft Movement and Harmonics
    • Countering Torsional Crank Motion and Harmonic Vibration
    • Construction
    • Engine Design, Materials & Other Factors
    • Identification
    • Maintenance
    • Effects of Removal
    • Original Invention
    • See Also

    The need for a damper will depend on the age of the engine design, its manufacture, strength of components, usable powerband, rev range and, most importantly,[citation needed] the quality of the engine's tune. The engine's tune especially in computer controlled applications can have a dramatic effect on durability,[citation needed] the aggressiveness of the tune puts the engine at risk of detonation which can be catastrophic to all rotating assembly components. Modern (roughly 1988+) DOHC, SOHC flat 4, flat 6, flat 8, and flat-plane V8 have no need for this device. With or without the presence of a damper, a crankshaft will act as a torsional spring to some extent. Impulses applied to the crankshaft by the connecting rods will "wind" this spring, which will respond (as a spring–mass system) by unwinding and re-winding in the opposite direction. This crankshaft winding will usually be damped out naturally. However, at certain crankshaft rotational speeds, such winding can overlap wit...

    Each time a cylinder fires, the force of the combustion is imparted to the crankshaft rod journal. The rod journal deflects in a torsional motion to some degree under this force. Harmonic vibrations result from the torsional motion imparted on the crankshaft. These harmonics are a function of many factors including frequencies created by the actual combustion and the natural frequencies the metals make under the stresses of combustion and flexing. In some engines, the torsional motion of the crankshaft at certain speeds can synchronize with the harmonic vibrations, causing a resonance. In some cases the resonance may stress the crankshaft to the point of cracking or complete failure.

    The harmonic balancer helps minimize torsional crankshaft harmonics and resonance. The damper is composed of two elements: an inertia massand an energy dissipating element. Most often made of rubber, this element may be composed of a synthetic elastomer, a clutch, a spring or fluid. The mass counteracts the torsional crank motions and in concert with the energy dissipating element absorbs the harmonics vibrations.

    An OEM damper consists of an outer mass bonded/vulcanized to an inner hub. An aftermarket performance damper consists of a mass which is attached/mounted to a housing (steel, aluminum, titanium, etc.) based on the different types of damper and where the mass is controlled differently. The first three use older technology; First is the liquid type damper which surrounds the mass immersed in the housing which is then bonded or welded together. Second is the o-ring type which surrounds the mass with a number of o-rings as it sits in its housing. Third is the friction type which has clutches and spring acting on the mass inside the outer housing. Fourth is the newest type in which the mass sits over and is attached an elastomer ring which is then attached to the outer housing. The crankshaft and damper together become (in its torsional response) a spring–mass–dampersystem again which can only occur by the two being interference fit together.

    Over time engine development has continually advanced in almost all areas from material, operation, and function. Many of the advances were led by the Japanese manufacturers as they have made quality and durability the cornerstone of their programs. The Japanese advanced the proliferation of forged crankshafts with rotating assemblies at 0 gram balance. Forged crankshafts are much stronger and are significantly less apt to exhibit detrimental torsional crankshaft movement which also mitigates harmonic frequencies. This progression has also seen the addition of forged rods and pistons initially in forced induction engines and more recently in normally aspirated engines. Adding these additional forged components ramps the engines rigidity reducing concern about crankshaft damage even further. With the advent of computer aided design and finite element analysis, manufacturers can now find and re-engineer weaker areas. Regardless of some of these improvements, certain engines, like the...

    The damper will be fitted at the front of the engine (opposite the clutch or transmission) just beyond the cover of the timing chain, gears, or belt, and behind the accessory drive pulley (which may carry one or more V, serpentine, or cogged belts.) In older vehicles the pulley and damper were separate units that were bolted together. In late model vehicles the two have been combined into one unit. Timing marks are almost always engraved for purposes of setting the ignition timing.

    OE dampers are predominantly made using rubber as the bonding agent between the inner hub and the outer mass. Rubber is susceptible to operational and environmental factors. Rubber only has a finite ability to withstand operating temperatures plus any fluids that may find their way onto the damper. They are also susceptible to low temperatures which can make the rubber brittle. Any cracking of the elastomer(rubber) would be an immediate indicator of the need to replace the unit. OE dampers must be balanced, unless acting as an external balancer (Harmonic Balancer), as the quality of materials (usually cast or sintered iron) do not lend themselves to acceptable/perfect balance specifications straight from manufacturing. Most aftermarket dampers are rebuildable, excluding the fluid type. When used in racing (drag, circle track, road race, etc.) they require regular inspection to ensure their proper function. When used on street driven vehicles, the damper manufacturer can provide insp...

    This will depend on a number of factors from quality of engine materials used to engine balance to the type of crankshaft design the quality of engine tune and more. Engines have continually improved in nearly all aspects but most importantly in quality of materials used and their manufacture (also discussed in Engine design, materials & other factors above). These improvements range from forged crankshafts, pistons and rods to other rotational components. Engine balance has also improved significantly through more advanced balancing techniques and the higher quality engine components which make the balancing process easier. Many OE manufacturers have been achieving 0 gram balance across their production since the 1980's. Crankshaft design is also a factor as cross plane crankshafts can be the most susceptible to internal harmonic damage. Flat plane crankshafts, I format and H format engines do not exhibit these issues but can reach extremely output and RPM levels where a harmonic d...

    Both Frederick Henry Royce and Frederick W. Lanchester have strong claims to the invention of the vibration damper, with the latest research showing Rolls-Royce using a crankshaft slipper (friction) vibration damper on their 1906 30HP models; however, Royce had not submitted it for patent. Lanchester had developed a theoretical multi-plate viscous design in 1910 (patent 21,139, 12 September 1910). Royce developed a viscous damper in 1912 that was then further developed and carried through to the B60 engine of the 1950s.

  3. Tuned mass damper - Wikipedia › wiki › Tuned_mass_damper
    • Principle
    • Mass Dampers in Automobiles
    • Mass Dampers in Spacecraft
    • Dampers in Power Transmission Lines
    • Dampers in Wind Turbines
    • Dampers in Buildings and Related Structures

    Tuned mass dampers stabilize against violent motion caused by harmonic vibration. They use a comparatively lightweight component to reduce the vibration of a system so that its worst-case vibrations are less intense. Roughly speaking, practical systems are tuned to either move the main mode away from a troubling excitation frequency, or to add damping to a resonance that is difficult or expensive to damp directly. An example of the latter is a crankshaft torsional damper. Mass dampers are frequently implemented with a frictional or hydraulic component that turns mechanical kinetic energy into heat, like an automotive shock absorber. Given a motor with mass m1 attached via motor mounts to the ground, the motor vibrates as it operates and the soft motor mounts act as a parallel spring and damper, k1 and c1. The force on the motor mounts is F0. In order to reduce the maximum force on the motor mounts as the motor operates over a range of speeds, a smaller mass, m2, is connected to m1 b...


    The tuned mass damper was introduced as part of the suspension system by Renault, on its 2005 F1 car (the Renault R25), at the 2005 Brazilian Grand Prix. The system was invented by Dr. Robin Tuluie, and it reportedly reduced lap times by 0.3 seconds: a phenomenal gain for a relatively simple device.The Stewards of the meeting deemed it legal, but the FIA appealed against that decision. Two weeks later, the FIA International Court of Appeal deemed the mass damper illegal. It was deemed to be i...

    Production cars

    Tuned mass dampers are widely used in production cars, typically on the crankshaft pulley to control torsional vibrationand, more rarely, the bending modes of the crankshaft. They are also used on the driveline for gearwhine, and elsewhere for other noises or vibrations on the exhaust, body, suspension or anywhere else. Almost all modern cars will have one mass damper, and some may have ten or more. The usual design of damper on the crankshaft consists of a thin band of rubber between the hub...

    One proposal to reduce vibration on NASA's Ares solid fuel booster was to use 16 tuned mass dampers as part of a design strategy to reduce peak loads from 6g to 0.25g, the TMDs being responsible for the reduction from 1g to 0.25g, the rest being done by conventional vibration isolatorsbetween the upper stages and the booster. Spin stabilized satellites have nutation development at specific frequencies. Eddy currentnutation dampers have flown on spin stabilized satellites to reduce and stabilize nutation.

    High-tension lines often have small barbell-shaped Stockbridge dampers hanging from the wires to reduce the high-frequency, low-amplitude oscillation termed flutter.

    A standard tuned mass damper for wind turbines consists of an auxiliary mass which is attached to the main structure by means of springs and dashpot elements. The natural frequency of the tuned mass damper is basically defined by its spring constant and the damping ratio determined by the dashpot. The tuned parameter of the tuned mass damper enables the auxiliary mass to oscillate with a phase shift with respect to the motion of the structure. In a typical configuration an auxiliary mass hung below the nacelle of a wind turbine supported by dampers or friction plates.

    Typically, the dampers are huge concrete blocks or steel bodies mounted in skyscrapers or other structures, and moved in opposition to the resonance frequency oscillations of the structure by means of springs, fluid or pendulums.

  4. Facebook - Wikipedia › wiki › Facebook

    Facebook's initial public offering came on May 17, 2012, at a share price of US$38. The company was valued at $104 billion, the largest valuation to that date. The IPO raised $16 billion, the third-largest in U.S. history, after Visa Inc. in ...

  5. Finite-state machine - Wikipedia › wiki › Finite-state_machine
    • Example: Coin-Operated Turnstile
    • Concepts and Terminology
    • Representations
    • Usage
    • Alternative Semantics
    • Mathematical Model
    • Optimization
    • Implementation
    • Further Reading
    • External Links

    An example of a simple mechanism that can be modeled by a state machine is a turnstile. A turnstile, used to control access to subways and amusement park rides is a gate with three rotating arms at waist height, one across the entryway. Initially the arms are locked, blocking the entry, preventing patrons from passing through. Depositing a coin or tokenin a slot on the turnstile unlocks the arms, allowing a single customer to push through. After the customer passes through, the arms are locked again until another coin is inserted. Considered as a state machine, the turnstile has two possible states: Locked and Unlocked. There are two possible inputs that affect its state: putting a coin in the slot (coin) and pushing the arm (push). In the locked state, pushing on the arm has no effect; no matter how many times the input push is given, it stays in the locked state. Putting a coin in – that is, giving the machine a coin input – shifts the state from Locked to Unlocked. In the unlocke...

    A state is a description of the status of a system that is waiting to execute a transition. A transition is a set of actions to be executed when a condition is fulfilled or when an event is received.For example, when using an audio system to listen to the radio (the system is in the "radio" state), receiving a "next" stimulus results in moving to the next station. When the system is in the "CD" state, the "next" stimulus results in moving to the next track. Identical stimuli trigger different actions depending on the current state. In some finite-state machine representations, it is also possible to associate actions with a state: 1. an entry action: performed when enteringthe state, and 2. an exit action: performed when exitingthe state.

    State/Event table

    Several state-transition table types are used. The most common representation is shown below: the combination of current state (e.g. B) and input (e.g. Y) shows the next state (e.g. C). The complete action's information is not directly described in the table and can only be added using footnotes.[further explanation needed] An FSM definition including the full action's information is possible using state tables (see also virtual finite-state machine).

    UML state machines

    The Unified Modeling Language has a notation for describing state machines. UML state machines overcome the limitations[citation needed] of traditional finite-state machines while retaining their main benefits. UML state machines introduce the new concepts of hierarchically nested states and orthogonal regions, while extending the notion of actions. UML state machines have the characteristics of both Mealy machines and Moore machines. They support actions that depend on both the state of the...

    SDL state machines

    The Specification and Description Language is a standard from ITUthat includes graphical symbols to describe actions in the transition: 1. send an event 2. receive an event 3. start a timer 4. cancel a timer 5. start another concurrent state machine 6. decision SDL embeds basic data types called "Abstract Data Types", an action language, and an execution semantic in order to make the finite-state machine executable.[citation needed]

    In addition to their use in modeling reactive systems presented here, finite-state machines are significant in many different areas, including electrical engineering, linguistics, computer science, philosophy, biology, mathematics, video game programming, and logic. Finite-state machines are a class of automata studied in automata theory and the theory of computation.In computer science, finite-state machines are widely used in modeling of application behavior, design of hardware digital systems, software engineering, compilers, network protocols, and the study of computation and languages.

    There are other sets of semantics available to represent state machines. For example, there are tools for modeling and designing logic for embedded controllers. They combine hierarchical state machines (which usually have more than one current state), flow graphs, and truth tables into one language, resulting in a different formalism and set of semantics. These charts, like Harel's original state machines, support hierarchically nested states, orthogonal regions, state actions, and transition actions.

    In accordance with the general classification, the following formal definitions are found. A deterministic finite-state machine or deterministic finite-state acceptor is a quintuple ( Σ , S , s 0 , δ , F ) {\\displaystyle (\\Sigma ,S,s_{0},\\delta ,F)} , where: 1. Σ {\\displaystyle \\Sigma } is the input alphabet(a finite non-empty set of symbols); 2. S {\\displaystyle S} is a finite non-empty set of states; 3. s 0 {\\displaystyle s_{0}} is an initial state, an element of S {\\displaystyle S} ; 4. δ {\\displaystyle \\delta } is the state-transition function: δ : S × Σ → S {\\displaystyle \\delta :S\\times \\Sigma \\rightarrow S} (in a nondeterministic finite automaton it would be δ : S × Σ → P ( S ) {\\displaystyle \\delta :S\\times \\Sigma \\rightarrow {\\mathcal {P}}(S)} , i.e. δ {\\displaystyle \\delta } would return a set of states); 5. F {\\displaystyle F} is the set of final states, a (possibly empty) subset of S {\\displaystyle S} . For both deterministic and non-deterministic FSMs, it is conventiona...

    Optimizing an FSM means finding a machine with the minimum number of states that performs the same function. The fastest known algorithm doing this is the Hopcroft minimization algorithm. Other techniques include using an implication table, or the Moore reduction procedure.Additionally, acyclic FSAs can be minimized in linear time.

    Hardware applications

    In a digital circuit, an FSM may be built using a programmable logic device, a programmable logic controller, logic gates and flip flops or relays. More specifically, a hardware implementation requires a register to store state variables, a block of combinational logic that determines the state transition, and a second block of combinational logic that determines the output of an FSM. One of the classic hardware implementations is the Richards controller. In a Medvedev machine, the output is...

    Software applications

    The following concepts are commonly used to build software applications with finite-state machines: 1. Automata-based programming 2. Event-driven finite-state machine 3. Virtual finite-state machine 4. State design pattern

    Finite-state machines and compilers

    Finite automata are often used in the frontend of programming language compilers. Such a frontend may comprise several finite-state machines that implement a lexical analyzerand a parser.Starting from a sequence of characters, the lexical analyzer builds a sequence of language tokens (such as reserved words, literals, and identifiers) from which the parser builds a syntax tree. The lexical analyzer and the parser handle the regular and context-free parts of the programming language's grammar.


    1. Sakarovitch, Jacques (2009). Elements of automata theory. Translated from the French by Reuben Thomas. Cambridge University Press. ISBN 978-0-521-84425-3. Zbl 1188.68177. 2. Wagner, F., "Modeling Software with Finite State Machines: A Practical Approach", Auerbach Publications, 2006, ISBN 0-8493-8086-3. 3. ITU-T, Recommendation Z.100 Specification and Description Language (SDL) 4. Samek, M., Practical Statecharts in C/C++, CMP Books, 2002, ISBN 1-57820-110-1. 5. Samek, M., Practical UML St...

    Finite-state machines (automata theory) in theoretical computer science

    1. Arbib, Michael A. (1969). Theories of Abstract Automata (1st ed.). Englewood Cliffs, N.J.: Prentice-Hall, Inc. ISBN 978-0-13-913368-8. 2. Bobrow, Leonard S.; Arbib, Michael A. (1974). Discrete Mathematics: Applied Algebra for Computer and Information Science (1st ed.). Philadelphia: W. B. Saunders Company, Inc. ISBN 978-0-7216-1768-8. 3. Booth, Taylor L. (1967). Sequential Machines and Automata Theory(1st ed.). New York: John Wiley and Sons, Inc. Library of Congress Card Catalog Number 67-...

    Abstract state machines in theoretical computer science

    1. Gurevich, Yuri (July 2000). "Sequential Abstract State Machines Capture Sequential Algorithms" (PDF). ACM Transactions on Computational Logic. 1 (1): 77–111. CiteSeerX doi:10.1145/343369.343384. S2CID 2031696.

  6. JTAG - Wikipedia › wiki › JTAG
    • History
    • Electrical Characteristics
    • Communications Model
    • Example: ARM11 Debug Tap
    • Common Extensions
    • Uses
    • Client Support
    • Similar Interface Standards
    • See Also
    • External Links

    In the 1988s, multi-layer circuit boards and integrated circuits (ICs) using ball grid array and similar mounting technologies were becoming standard, and connections were being made between ICs that were not available to probes. The majority of manufacturing and field faults in circuit boards were due to poor solderjoints on the boards, imperfections among board connections, or the bonds and bond wires from IC pads to pin lead frames. The Joint Test Action Group (JTAG) was formed in 1985 to provide a pins-out view from one IC pad to another so these faults could be discovered. The industry standard became an IEEE standard in 1990 as IEEE Std. 1149.1-1990 after many years of initial use. In the same year, Intel released their first processor with JTAG (the 80486) which led to quicker industry adoption by all manufacturers. In 1994, a supplement that contains a description of the boundary scan description language (BSDL) was added. Further refinements regarding the use of all-zeros f...

    A JTAG interface is a special interface added to a chip. Depending on the version of JTAG, two, four, or five pins are added. The four and five pin interfaces are designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met. The two pin interface is designed so that multiple chips can be connected in a star topology. In either case a test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board.

    In JTAG, devices expose one or more test access ports (TAPs). The picture above shows three TAPs, which might be individual chips or might be modules inside one chip. A daisy chain of TAPs is called a scan chain, or (loosely) a target. Scan chains can be arbitrarily long, but in practice twenty TAPs is unusually long.[citation needed] To use JTAG, a host is connected to the target's JTAG signals (TMS, TCK, TDI, TDO, etc.) through some kind of JTAG adapter, which may need to handle issues like level shifting and galvanic isolation. The adapter connects to the host using some interface such as USB, PCI, Ethernet, and so forth.

    An example helps show the operation of JTAG in real systems. The example here is the debug TAP of an ARM11 processor, the ARM1136core. The processor itself has extensive JTAG capability, similar to what is found in other CPU cores, and it is integrated into chips with even more extensive capabilities accessed through JTAG. This is a non-trivial example, which is representative of a significant cross section of JTAG-enabled systems. In addition, it shows how control mechanisms are built using JTAG's register read/write primitives, and how those combine to facilitate testing and debugging complex logic elements; CPUs are common, but FPGAs and ASICsinclude other complex elements which need to be debugged. Licensees of this core integrate it into chips, usually combining it with other TAPs as well as numerous peripherals and memory. One of those other TAPs handles boundary scan testing for the whole chip; it is not supported by the debug TAP. Examples of such chips include: 1. The OMAP2...

    Microprocessor vendors have often defined their own core-specific debugging extensions. Such vendors include Infineon, MIPS with EJTAG, and more. If the vendor does not adopt a standard (such as the ones used by ARM processors; or Nexus), they need to define their own solution. If they support boundary scan, they generally build debugging over JTAG. Freescale has COP and OnCE (On-Chip Emulation). OnCE includes a JTAG command which makes a TAP enter a special mode where the IR holds OnCE debugging commands for operations such as single stepping, breakpointing, and accessing registers or memory. It also defines EOnCE (Enhanced On-Chip Emulation)presented as addressing real time concerns. ARMhas an extensive processor core debug architecture (CoreSight) that started with EmbeddedICE (a debug facility available on most ARM cores), and now includes many additional components such as an ETM (Embedded Trace Macrocell), with a high speed trace port, supporting multi-core and multithread tra...

    Except for some of the very lowest end systems, essentially all embedded systems platforms have a JTAG port to support in-circuit debugging and firmware programming as well as for boundary scan tes...
    The PCI bus connector standard contains optional JTAG signals on pins 1–5; PCI Express contains JTAG signals on pins 5–9. A special JTAG card can be used to reflash a corrupt BIOS.
    Boundary scan testing and in-system (device) programming applications are sometimes programmed using the Serial Vector Format, a textual representation of JTAG operations using a simple syntax. Oth...
    As mentioned, many boards include JTAG connectors, or just pads, to support manufacturing operations, where boundary scan testing helps verify board quality (identifying bad solder joints, etc.) an...

    The target's JTAG interface is accessed using some JTAG-enabled application and some JTAG adapter hardware. There is a wide range of such hardware, optimized for purposes such as production testing, debugging high speed systems, low cost microcontroller development, and so on. In the same way, the software used to drive such hardware can be quite varied. Software developers mostly use JTAG for debugging and updating firmware.

    Serial Wire Debug (SWD) is an alternative 2-pin electrical interface that uses the same protocol. It uses the existing GND connection. SWD uses an ARM CPU standard bi-directional wire protocol, defined in the ARM Debug Interface v5. This enables the debugger to become another AMBA bus master for access to system memory and peripheral or debug registers. Data rate is up to 4 MB/s at 50 MHz. SWD also has built-in error detection. On JTAG devices with SWD capability, the TMS and TCK are used as SWDIO and SWCLK signals, providing for dual-mode programmers.

  7. Denial-of-service attack - Wikipedia › wiki › Denial-of-service_attack
    • History
    • Types
    • Symptoms
    • Attack Techniques
    • Defense Techniques
    • Unintentional Denial-Of-Service
    • Side Effects of Attacks
    • Legality
    • External Links

    Panix, the third-oldest ISP in the world, was the target of what is thought to be the first DoS attack. On September 6, 1996, Panix was subject to a SYN floodattack which brought down its services for several days while hardware vendors, notably Cisco, figured out a proper defense. Another early demonstration of DoS attack was made by Khan C. Smith in 1997 during a DEF CON event, disrupting Internet access to the Las Vegas Strip for over an hour. The release of sample code during the event led to the online attack of Sprint, EarthLink, E-Trade, and other major corporations in the year to follow. On March 5, 2018, an unnamed customer of the US-based service provider Arbor Networks fell victim to the largest DDoS to that date, reaching a peak of about 1.7 terabits per second. The previous record had been set a few days earlier, on March 1, 2018, when GitHub was hit by an attack of 1.35 terabits per second. In February 2020, Amazon Web Services experienced an attack with a peak volume...

    Denial-of-service attacks are characterized by an explicit attempt by attackers to prevent legitimate use of a service. There are two general forms of DoS attacks: those that crash services and those that flood services. The most serious attacks are distributed.

    The United States Computer Emergency Readiness Team(US-CERT) has identified symptoms of a denial-of-service attack to include: 1. unusually slow network performance(opening files or accessing web sites), 2. unavailability of a particular web site, or 3. inability to access any web site.

    Attack tools

    In cases such as MyDoom and Slowloris the tools are embedded in malware and launch their attacks without the knowledge of the system owner. Stacheldraht is a classic example of a DDoS tool. It uses a layered structure where the attacker uses a client program to connect to handlers which are compromised systems that issue commands to the zombie agentswhich in turn facilitate the DDoS attack. Agents are compromised via the handlers by the attacker using automated routines to exploit vulnerabili...

    Application-layer attacks

    Application-layer attacks employ DoS-causing exploits and can cause server-running software to fill the disk space or consume all available memory or CPU time. Attacks may use specific packet types or connection requests to saturate finite resources by, for example, occupying the maximum number of open connections or filling the victim's disk space with logs. An attacker with shell-level access to a victim's computer may slow it until it is unusable or crash it by using a fork bomb. Another k...

    Degradation-of-service attacks

    Pulsing zombies are compromised computers that are directed to launch intermittent and short-lived floodings of victim websites with the intent of merely slowing it rather than crashing it. This type of attack, referred to as degradation-of-service, can be more difficult to detect and can disrupt and hamper connection to websites for prolonged periods of time, potentially causing more overall disruption than a denial-of-service attack.Exposure of degradation-of-service attacks is complicated...

    Defensive responses to denial-of-service attacks typically involve the use of a combination of attack detection, traffic classification and response tools, aiming to block traffic that they identify as illegitimate and allow traffic that they identify as legitimate.A list of prevention and response tools is provided below:

    An unintentional denial-of-service can occur when a system ends up denied, not due to a deliberate attack by a single individual or group of individuals, but simply due to a sudden enormous spike in popularity. This can happen when an extremely popular website posts a prominent link to a second, less well-prepared site, for example, as part of a news story. The result is that a significant proportion of the primary site's regular users – potentially hundreds of thousands of people – click that link in the space of a few hours, having the same effect on the target website as a DDoS attack. A VIPDoS is the same, but specifically when the link was posted by a celebrity. When Michael Jackson died in 2009, websites such as Google and Twitter slowed down or even crashed. Many sites' servers thought the requests were from a virus or spyware trying to cause a denial-of-service attack, warning users that their queries looked like "automated requests from a computer virusor spyware applicatio...


    In computer network security, backscatter is a side-effect of a spoofed denial-of-service attack. In this kind of attack, the attacker spoofs (or forges) the source address in IP packetssent to the victim. In general, the victim machine cannot distinguish between the spoofed packets and legitimate packets, so the victim responds to the spoofed packets as it normally would. These response packets are known as backscatter. If the attacker is spoofing source addresses randomly, the backscatter r...

    Many jurisdictions have laws under which denial-of-service attacks are illegal. 1. In the US, denial-of-service attacks may be considered a federal crime under the Computer Fraud and Abuse Act with penalties that include years of imprisonment. The Computer Crime and Intellectual Property Section of the US Department of Justicehandles cases of DoS and DDoS. In one example, in July 2019, Austin Thompson, aka DerpTrolling, was sentenced to 27 months in prison and $95,000 restitution by a federal court for conducting multiple DDoS attacks on major video gaming companies, disrupting their systems from hours to days. 2. In European countries, committing criminal denial-of-service attacks may, as a minimum, lead to arrest. The United Kingdom is unusual in that it specifically outlawed denial-of-service attacks and set a maximum penalty of 10 years in prison with the Police and Justice Act 2006, which amended Section 3 of the Computer Misuse Act 1990. 3. In January 2019, Europol announced t...

  8. Central processing unit - Wikipedia › wiki › Central_processing_unit
    • History
    • Operation
    • Structure and Implementation
    • Virtual CPUs
    • Performance
    • External Links

    Early computers such as the ENIAC had to be physically rewired to perform different tasks, which caused these machines to be called "fixed-program computers". The "central processing unit" term has been in use since as early as 1955. Since the term "CPU" is generally defined as a device for software (computer program) execution, the earliest devices that could rightly be called CPUs came with the advent of the stored-program computer. The idea of a stored-program computer had been already present in the design of J. Presper Eckert and John William Mauchly's ENIAC, but was initially omitted so that it could be finished sooner. On June 30, 1945, before ENIAC was made, mathematician John von Neumann distributed the paper entitled First Draft of a Report on the EDVAC. It was the outline of a stored-program computer that would eventually be completed in August 1949. EDVAC was designed to perform a certain number of instructions (or operations) of various types. Significantly, the program...

    The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored instructions that is called a program. The instructions to be executed are kept in some kind of computer memory. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the instruction cycle. After the execution of an instruction, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the program counter. If a jump instruction was executed, the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally. In more complex CPUs, multiple instructions can be fetched, decoded and executed simultaneously. This section describes what is generally referred to as the "classic RISC pipeline", which is quite common among the simple CPUs used in many electronic...

    Hardwired into a CPU's circuitry is a set of basic operations it can perform, called an instruction set. Such operations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping to a different part of a program. Each basic operation is represented by a particular combination of bits, known as the machine language opcode; while executing instructions in a machine language program, the CPU decides which operation to perform by "decoding" the opcode. A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify arguments for the operation (for example, the numbers to be summed in the case of an addition operation). Going up the complexity scale, a machine language program is a collection of machine language instructions that the CPU executes. The actual mathematical operation for each instruction is performed by a combinational logic circuit within the CPU's processor known as the arithmetic logic un...

    Cloud computing can involve subdividing CPU operation into virtual central processing units (vCPUs). A host is the virtual equivalent of a physical machine, on which a virtual system is operating. When there are several physical machines operating in tandem and managed as a whole, the grouped computing and memory resources form a cluster. In some systems, it is possible to dynamically add and remove from a cluster. Resources available at a host and cluster level can be partitioned out into resources pools with fine granularity.

    The performance or speed of a processor depends on, among many other factors, the clock rate (generally given in multiples of hertz) and the instructions per clock (IPC), which together are the factors for the instructions per second (IPS) that the CPU can perform.Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the memory hierarchy also greatly affects processor performance, an issue barely considered in MIPS calculations. Because of these problems, various standardized tests, often called "benchmarks" for this purpose‍—‌such as SPECint‍—‌have been developed to attempt to measure the real effective performance in commonly used applications. Processing performance of computers is increased by using multi-core processors, which essentially is plugging two or more indiv...

    How Microprocessors Work at HowStuffWorks.
    25 Microchips that shook the world – an article by the Institute of Electrical and Electronics Engineers.
  9. The S.O.U.L. S.Y.S.T.E.M. - Wikipedia › wiki › The_S

    The S.O.U.L. S.Y.S.T.E.M. was an American R&B and dance music group, assembled by Robert Clivillés and David Cole of C&C Music Factory, that was active in 1992. The group featured lead vocals by Michelle Visage, who was formerly a member ...

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